Technology Field
The present invention relates to a data writing method, and in particular, a data writing method for a rewritable non-volatile memory module and a memory control circuit unit and a memory storage apparatus using the method.
Description of Related Art
As digital cameras, mobile phones, and MP3 players have been growing rapidly in recent years, consumers' demand for storage media has also been growing significantly. With characteristics including data non-volatility, energy saving, small size, lack of mechanical structures, high reading/writing speed, etc., rewritable non-volatile memories are most suitable for portable electronic products, such as laptops. A solid state drive is a memory storage apparatus which utilizes a flash memory as its storage medium. Therefore, the flash memory industry has become a popular line among the electronics industries.
According to the number of bits that can be stored in each memory cell, the NAND flash memory may be classified into a single level cell (SLC) NAND flash memory, a multi level cell (MLC) NAND flash memory, and a trinary level cell (TLC) NAND flash memory. Specifically, each memory cell in the SLC NAND flash memory stores 1 bit of data (i.e., “1” or “0”), each memory cell in the MLC NAND flash memory stores 2 bits of data, and each memory cell in the TLC NAND flash memory stores three bits of data.
In the NAND flash memory, a physical programming unit is constituted by several memory cells arranged on a same word line. Since each memory cell in the SLC NAND flash memory is capable of storing 1 bit of data, the several memory cells arranged on the same word line in the SLC NAND flash memory correspond to one physical programming unit.
In contrast with the SLC NAND flash memory, a floating gate storage layer in each memory cell of the MLC NAND flash memory is capable of storing 2 bits of data, wherein each storage state (i.e., “11”, “10”, “01”, and “00”) includes the least significant bit (LSB) and the most significant bit (MSB). For example, in the storage state, the value of the first bit counted from the left is the LSB, and the value of the second bit counted from the left is the MSB. Accordingly, the several memory cells arranged on the same word line may constitute two physical programming units, wherein the physical programming unit constituted by the LSBs of the memory cells is referred to as a lower physical programming unit, and the physical programming unit constituted by the MSBs of the memory cells is referred to as an upper physical programming unit. In particular, the writing speed of the lower physical programming unit is faster than the writing speed of the upper physical programming unit, and when a failure occurs in the process of programming the upper physical programming unit, the data stored in the lower physical programming unit may be lost.
Similarly, each memory cell in the TLC NAND flash memory can store 3 bits of data, wherein each storage state (i.e., “111”, “110”, “101”, “100”, “011”, “010”, “001”, or “000”) includes the first bit (i.e., the LSB) counted from the left, the second bit (i.e., the center significant bit, CSB) counted from the left, and the third bit (i.e., the MSB) counted from the left. Accordingly, the several memory cells arranged on the same word line may constitute three physical programming units, wherein the physical programming unit constituted by the LSBs of the memory cells is referred to as a lower physical programming unit, the physical programming unit constituted by the CSBs of the memory cells is referred to as a middle physical programming unit, and the physical programming unit constituted by the MSBs of the memory cells is referred to as an upper physical programming unit. In particular, in the TLC NAND flash memory, to ensure that the data on a word line can be stably stored, it is necessary to program the word line for three times. For example, after performing a first programming on the memory cells on a first word line, the memory cells on the first word line are in a first state. When the memory cells on a second word line are programmed, the memory cells on the first word line are simultaneously programmed again. At this time, the memory cells on the first word line are in a foggy state. Then, when the memory cells on a third word line are programmed, the memory cells on the first and second word lines are simultaneously programmed again. At this time, the memory cells on the first word line are in a fine state. Furthermore, when the memory cells on a fourth word line are programmed, the memory cells on the second and third word lines are simultaneously programmed again. At this time, the memory cells on the second word line are in a fine state. Thereby, it can be ensured that the data in the memory cells on the first word line are stably stored. In light of the principle above, when a host system issues a flush command, to ensure that the data are already stably stored to the TLC NAND flash memory, a memory controller needs to further continue to program three other word lines. Each word line includes three physical programming units. Therefore, a memory control circuit needs to write virtual data to 9 physical programming units, which accordingly causes excessive redundant writings, lowers storage efficiency of the memory storage apparatus, and shortens the lifespan of the memory storage apparatus.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.